module tb_mux4_1;

	reg InA;
	reg InB;
	reg InC;
	reg InD;
	reg [1:0] S;
	wire Out;
	reg [2:0] i;

	mux4_1 DUB(.InA(InA), .InB(InB),.InC(InC),.InD(InD), .S(S), .Out(Out));
	initial
	begin 
	    for(i=3'b000; i != 3'b100; i=i+1'b1) begin

	      #10  S= i[1:0];
             
	  	InA = 1'b0;
	  	InB = 1'b0;
	  	InC = 1'b0;
	  	InD = 1'b0;
	
          	#10 InA = 1'b1;
	      	InB = 1'b0;
	      	InC = 1'b0;
	      	InD = 1'b0;
	
          	#10 InA = 1'b0;
	      	InB = 1'b1;
	      	InC = 1'b0;
	      	InD = 1'b0;
	 	 
          	#10 InA = 1'b1;
	      	InB = 1'b1;
	      	InC = 1'b0;
	      	InD = 1'b0;
	
	 	#10  InA = 1'b0;
	      	InB = 1'b0;
	      	InC = 1'b1;
	      	InD = 1'b0;
	
          	#10 InA = 1'b1;
	      	InB = 1'b0;
	      	InC = 1'b1;
	      	InD = 1'b0;
	
          	#10 InA = 1'b0;
	      	InB = 1'b1;
	      	InC = 1'b1;
	      	InD = 1'b0;
	  
          	#10 InA = 1'b1;
	      	InB = 1'b1;
	      	InC = 1'b1;
	      	InD = 1'b0;
	
	 	#10  InA = 1'b0;
	      	InB = 1'b0;
	      	InC = 1'b0;
	      	InD = 1'b1;
	
          	#10 InA = 1'b1;
	      	InB = 1'b0;
	      	InC = 1'b0;
	      	InD = 1'b1;
	
          	#10 InA = 1'b0;
	      	InB = 1'b1;
	      	InC = 1'b0;
	      	InD = 1'b1;
	 	 
          	#10 InA = 1'b1;
	      	InB = 1'b1;
	      	InC = 1'b0;
	      	InD = 1'b1;
	
	 	#10  InA = 1'b0;
	      	InB = 1'b0;
	      	InC = 1'b1;
	      	InD = 1'b1;
	
          	#10 InA = 1'b1;
	      	InB = 1'b0;
	      	InC = 1'b1;
	      	InD = 1'b1;
	
          	#10 InA = 1'b0;
	      	InB = 1'b1;
	      	InC = 1'b1;
	      	InD = 1'b1;
	 	 
          	#10 InA = 1'b1;
	      	InB = 1'b1;
	      	InC = 1'b1;
	      	InD = 1'b1;
	   	end
	end

	//Output monitors

     always@(S, InA, InB, InC, InD, Out)
	begin
	     #5
	     case(S)
		2'b00 : $display("Expecting InA : %b, Got %b", InA, Out);
		2'b01 : $display("Expecting InB : %b, Got %b", InB, Out);
		2'b10 : $display("Expecting InC : %b, Got %b", InC, Out);
		2'b11 : $display("Expecting InD : %b, Got %b", InD, Out);
	     endcase
	end
endmodule

